To provide a non volatile semiconductor memory device for making an application voltage at the time of writing data lower than that in conventional channel hot electron injection by providing a memory transistor with a single layer gate structure for injecting hot electrons due to ionization collision, for example, secondary ionization collision into a floating gate, for improving the injecting efficiency of the hot electrons at the time of providing a high concentration channel area, and for reducing a voltage and a method for injecting the charge.

This non volatile semiconductor memory device is provided with a floating gate 29 constituted of a single polysilicon layer, two source/drain areas 23 and 24, a control gate 30 constituted of an impurity area formed in a p-type well 21 and a voltage supply circuit. The voltage supply circuit supplies a write drain voltage to the two source/drain areas 23 and 24 at the time of writing data, and supplies a write gate voltage to the control gate 30. Thus, it is possible to inject hot electron HE due to secondary ionization collision generated at the source/drain area 24 side serving as the drain to the flowing gate 29.