Title:
ノッチゲートを利用したローカルSONOS構造を有する不揮発性半導体メモリ素子及びその製造方法
Document Type and Number:
Japanese Patent JP4417145
Kind Code:
B2
Abstract:
Silicon-oxide-nitride-oxide-silicon (SONOS) transistor with a slotted grid comprises: (a) a substrate (602) having some source and drain regions (612, 636); (b) a grid insulating layer (608) on the substrate between the source and drain regions; (c) a slotted grid structure (606), on the grid insulating layer, having at least one slot (605); and (d) at least one corner oxide-nitride-oxide (ONO) structure (622, 624, 622) respectively in the slot(s) of the grid structure. An independent claim is also included for the fabrication of a slotted grid structure for a SONOS transistor.
Inventors:
Kim Soshu
Lee Rai
Be bell
Kim Chur
Lee Kasei
Lee Rai
Be bell
Kim Chur
Lee Kasei
Application Number:
JP2004074682A
Publication Date:
February 17, 2010
Filing Date:
March 16, 2004
Export Citation:
Assignee:
SAMSUNG ELECTRONICS CO.,LTD.
International Classes:
H01L21/8247; H01L21/28; H01L21/336; H01L27/115; H01L29/423; H01L29/78; H01L29/788; H01L29/792
Domestic Patent References:
| JP10098111A | ||||
| JP2001156188A | ||||
| JP2002280548A | ||||
| JP6151833A |
Foreign References:
| US5834817 | ||||
| WO2003044868A1 |
Attorney, Agent or Firm:
Masatake Shiga
Takashi Watanabe
Takashi Watanabe