To improve reliability for write protection in a non-selective NAND train by applying a voltage which is sufficiently capable of ON state even in a normally OFF state and selective automatic boost of the channel potential on the control gate of each of the selected memory cells, the neighboring memories, and the memory cells sharing a control gate.

The control gates of memory cells selected ones with a circular mark, the neighboring one and the other ones are impressed with 20V, 4.5V and 11V. With this voltage control, the selected transistor SG 1 is made OFF by 3.3V supplied from a non-selective bit line BL2 to generate automatic boost. Accordingly the potential of the control gate of the memory cell impressed with 4.5V becomes lower than the channel potential and made OFF to provide a write operation. The potentials of the channel regions 2, 1 and 3 of the memory cells are raised to 10V, 7V in response to the rise of the voltage from 0V to 20V, and from 0V to 11V, diminishing the potential difference. Therefore, stress applied to memory cells are mitigated, improving reliability.