To solve such a problem that read and write cycles of a memory cell takes double time when a memory cell in which two bits/cell is stored is used and to provide a peripheral control circuit having memory array constitution in which area can be reduced.
Each memory is connected through a common bit line in which two cells are a drain or a source, and a memory array is constituted by arranging a plurality of unit memory arrays of this two cells. And write or read can be performed by simultaneous one time access for a plurality of bites by replacing bit arrangement of a memory cell array by a write method or a read method. Also, operation speed is increased by providing a sensor amplifier which is not pre-charged as further increasing read speed.
YOSHIKI HIROSHI
KAMIGAKI YOSHIAKI
KATAYAMA KOZO
MINAMI SHINICHI
KANAI TAKEO
HITACHI ULSI SYS CO LTD
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