Title:
NON-VOLATILE SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JPH01159896
Kind Code:
A
Abstract:
PURPOSE:To cause the source line of a memory transistor selected by means of one control gate line to be common by deciding respective column latches, conduction and non-conduction between bit lines according to a control signal by means of a switching means. CONSTITUTION:The deleting cycle of an internal writing cycle is executed in the setting in which a signal CLK1 maintains an 'H' level, a signal CLK2 is made to fall to an 'L' level, a high voltage source VPP1 is rised to a high voltage level, and a high voltage source VPP2 maintains a grounding level. By the signal setting, an interruption between a column latch 1 and a bit line BL is executed, a column latch 2 and a control gate line CGL maintain a connecting condition, and only a high voltage switch 3 of the control gate line CGL is activated. For such a reason, even when a source line SL of a memory transistor MQ selected by the control gate CGL is made common, an interference between column latch 1 through the mutual bit lines BL is not generated, the latch data of the column latch 1 cannot be destroyed, and a non-volatile writing can be correctly executed.
Inventors:
TERADA YASUSHI
NAKAYAMA TAKESHI
HAYASHIKOSHI MASANORI
MIYAWAKI YOSHIKAZU
KOBAYASHI KAZUO
NAKAYAMA TAKESHI
HAYASHIKOSHI MASANORI
MIYAWAKI YOSHIKAZU
KOBAYASHI KAZUO
Application Number:
JP32213887A
Publication Date:
June 22, 1989
Filing Date:
December 17, 1987
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G11C7/00; G11C16/06; G11C17/00; H01L21/8246; H01L21/8247; H01L27/10; H01L27/112; H01L29/78; H01L29/788; H01L29/792; (IPC1-7): G11C7/00; G11C17/00; H01L27/10; H01L29/78
Domestic Patent References:
| JPS61184795A | 1986-08-18 |
Attorney, Agent or Firm:
Kaneo Miyata (3 outside)
Previous Patent: METHOD FOR WRITING DATA IN ELECTRICALLY-WRITABLE NON-VOLATILE MEMORY
Next Patent: OBJECT SUPPLY DEVICE
Next Patent: OBJECT SUPPLY DEVICE