PURPOSE: To improve an erasing rate at the erasure of information by a method wherein at least a part of a region, where a floating gate electrode of a memory cell transistor and a diffusion layer region of a semiconductor substrate are close to each other, is not covered with an above metal wiring layer.

CONSTITUTION: A metal wiring 9 is a bit line which is connected (represented by a contact section 9') to a drain region or a source region 7 through the intermediary of the contact hole provided in an interlaminar insulating layer 8. At this point, the metal wiring 9 is provided aside so as not to cover at least a part 10 of the region where a floating gate electrode 4 and a diffusion layer region 7 of a semiconductor substrate 1 are close to each other. Ultraviolet rays 28 irradiated for erasure of information are made to be incident directly at least on the part 10 of the region where the floating gate electrode 4 and the diffusion layer region 7 of the semiconductor substrate 1 are close to each other, so that electrons discharged to the diffusion layer region 7 side jumping over a barrier of a gate insulating film 3 between the floating gate electrode 4 and the diffusion layer region 7 increase in number and consequently the erasing rate can be improved.