PURPOSE: To eliminate a drop in the drain voltage of a memory cell at the time of writing data, to make strong to the unevenness in a process and to write the data at high speed by using a booster circuit as a power switching circuit and applying this voltage to the buffer of a decoder.
CONSTITUTION: At the time of an ordinary reading, the same voltage as VCC is impressed to the voltage of a source VPP, signals -W, HD, -HD are respectively logics '1', '0', '1', a transistor T37 is turned on and the output of a node SW1 has the same voltage as the VCC. On the other hand, at the time of writing the data, a higher voltage than the power source VCC is impressed to the power source VPP. The signals -W, HD, -HD go to the logics '0', '1', '0'. Accordingly, a signal from a ring oscillator constituted of inverters I2WI6 is applied to an inverter consisting of transistors T23WT25 and the buffer consisting of transistors T26WT28 through an inverter I7, the potential of the node SW1 is raised for every clock pulse and finally, stable at a voltage higher by the threshold voltage of the transistor T36 than the power source VPP.
IWAHASHI HIROSHI
ASANO MASAMICHI
SUZUKI KAZUTO
KUMAGAI SHIGERU
SATO ISAO
TOSBAC COMPUTER SYSTEM CO LTD
TOSHIBA MICRO CUMPUTER ENG
| JPS59185091A | 1984-10-20 | |||
| JPS57143795A | 1982-09-06 | |||
| JPS57130293A | 1982-08-12 |
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