Title:
不揮発性半導体記憶装置
Document Type and Number:
Japanese Patent JP4088323
Kind Code:
B1
Abstract:
Provided is a nonvolatile semiconductor device capable of performing writing operations of different resistance changes for memory cells having variable resistive elements whose resistive characteristics are changed by voltage applications, individually and simultaneously. The device includes: a load resistive characteristic variable circuit for each bit line connected commonly with the memory cells on the same column for selecting one of two load resistive characteristics according to a first writing operation where the resistive characteristics of the variable resistive element to be written transit from a low resistance state to a high resistance state or a second writing operation where they transit reversely; and a writing voltage pulse application circuit for applying a first voltage pulse in a first writing operation and a second voltage pulse in a second writing operation to the memory cells to be written through the load resistive characteristic variable circuits and the bit limes.
Inventors:
Go Inoue
Yasunari Hosoi
Shigeo Onishi
Nobuyoshi Awaya
Yasunari Hosoi
Shigeo Onishi
Nobuyoshi Awaya
Application Number:
JP2006330045A
Publication Date:
May 21, 2008
Filing Date:
December 06, 2006
Export Citation:
Assignee:
Sharp Corporation
International Classes:
G11C13/00; H01L27/10; H01L45/00; H01L49/00
Domestic Patent References:
| JP2006099882A | ||||
| JP2006203098A | ||||
| JP2006190376A |
Attorney, Agent or Firm:
Yoshifumi Masaki