Title:
不揮発性半導体記憶装置
Document Type and Number:
Japanese Patent JP4424952
Kind Code:
B2
Abstract:
Until the number of pulse application n reaches 12, as a first-half pulse, a pulse is set to have a width fixed to 2 ms, and its voltage is increased every time. As a latter-half pulse, the pulse is set to have a width fixed to 3 ms and the pulse voltage is increased every time until the maximum voltage is attained. After the maximum voltage is attained, first, the pulse of a width of 3 ms is applied twice, the pulse of a width of 4 ms with the maximum voltage is applied twice, and the pulse of a width of 5 ms with the maximum voltage is applied twice. Even after the maximum voltage is attained, change over time of a threshold voltage can be more linear. Thus, a non-volatile semiconductor memory device allowing efficient programming operation and erasing operation in a short period of time can be provided.
Inventors:
Hidenori Mitani
Fumihiko Nitta
Tadaaki Yamauchi
Taku Ogura
Fumihiko Nitta
Tadaaki Yamauchi
Taku Ogura
Application Number:
JP2003322643A
Publication Date:
March 03, 2010
Filing Date:
September 16, 2003
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G11C16/02; G11C7/00; G11C16/06; G11C16/10; G11C16/14; G11C16/16; G11C16/22; G11C16/30; G11C16/34; G11C29/00
Domestic Patent References:
| JP2002367380A | ||||
| JP2003085987A | ||||
| JP2000049314A | ||||
| JP2002025279A | ||||
| JP11039887A | ||||
| JP2002150785A |
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai