Title:
不揮発性半導体記憶装置
Document Type and Number:
Japanese Patent JP5172269
Kind Code:
B2
Abstract:
A nonvolatile semiconductor memory device comprises a memory cell array of electrically erasable programmable nonvolatile memory cells arranged in matrix, each memory cell using a variable resistor. A pulse generator is operative to generate plural types of write pulses for varying the resistance of the variable resistor in three or more stages based on ternary or higher write data. A selection circuit is operative to select a write target memory cell from the memory cell array based on a write address and supply the write pulse generated from the pulse generator to the selected memory cell.
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Inventors:
Hiroyuki Nagashima
Hirofumi Inoue
Haruki Toda
Hirofumi Inoue
Haruki Toda
Application Number:
JP2007269770A
Publication Date:
March 27, 2013
Filing Date:
October 17, 2007
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G11C13/00; H01L27/10; H01L27/105; H01L45/00; H01L49/00
Domestic Patent References:
| JP2004185756A | ||||
| JP2003100085A | ||||
| JP2007184591A | ||||
| JP2006351061A | ||||
| JP2006514440A | ||||
| JP2007164964A | ||||
| JP2005235360A | ||||
| JP2007018681A | ||||
| JP2004319587A |
Attorney, Agent or Firm:
Masaru Itami
Kazuhiko Tamura
Kazuhiko Tamura