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Title:
NON-VOLATILE STORAGE DEVICE
Document Type and Number:
Japanese Patent JP2008305429
Kind Code:
A
Abstract:

To easily connect chip selection signal output terminals of first semiconductor integrated circuit chips respectively to chip selection signal input terminals of corresponding non-volatile memory chips by means of bonding wires without being disturbed by other bonding wire.

Terminals (chip selection signal input terminals CE) for inputting chip selection signals from the first semiconductor integrated circuit chips 33 are positioned at the end of an external terminal array, and a plurality of non-volatile memory chips 34a and 34b are laminated by being shifted alternately in the crossing directions. In this way, external terminals of the laminated non-volatile memory chips are individually exposed for wire bonding.


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Inventors:
NISHIZAWA HIROTAKA
YUGAWA YOSUKE
TOTSUKA TAKASHI
Application Number:
JP2008203888A
Publication Date:
December 18, 2008
Filing Date:
August 07, 2008
Export Citation:
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Assignee:
RENESAS TECH CORP
International Classes:
G06K19/077
Domestic Patent References:
JPH08190615A1996-07-23
JPH10173125A1998-06-26
JPH08129627A1996-05-21
JPH08138022A1996-05-31
JPS6294394A1987-04-30
JPS6444171A1989-02-16
JP2001511408A2001-08-14
Foreign References:
WO1999006107A11999-02-11
Attorney, Agent or Firm:
Shizuyo Tamamura



 
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