Title:
NONOVERLAPPING SIGNAL GENERATION CIRCUIT FOR SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JP2668660
Kind Code:
B2
Abstract:
PURPOSE: To obtain an nonoverlapping signal generation circuit operable at a high rate through simple structure by shifting the charging time and the discharge time through the use of a complementary transistor(TR) connected in series with an inverter.
CONSTITUTION: When an input makes a transition from 0 to 1, for example, an nTR 20 connected with the output of an inverter 16 is turned off by the output 1 from an inverter 14 through a nonoverlapping circuit 30 and a node W1 is charged through a pTR 18 having a gate being turned on with a ground potential Vss and thereby an output A goes 1. On the other hand, an nTR 26 connected in series with a pTR 24 through an inverter 22 is turned on and a node N2 is discharged to the ground potential Vss and thereby an output anti-A goes 0. Since the discharge is carried out quicker than the charging, the output A and the output anti-A produce a nonoverlapping signal. Consequently, a nonoverlapping signal generation circuit operable at a high rate can be realized through simple circuitry.
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Inventors:
Cui together
Application Number:
JP3220095A
Publication Date:
October 27, 1997
Filing Date:
February 21, 1995
Export Citation:
Assignee:
EL G SEMICON Company Limited
International Classes:
G11C11/409; G11C11/407; G11C11/408; G11C11/413; H03K5/151; H03K19/0175; (IPC1-7): G11C11/408; G11C11/413; H03K19/0175
Domestic Patent References:
| JP2131616A |
Attorney, Agent or Firm:
Fukami Hisaro (3 outside)
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