Title:
NONVOLATILE MEMORY
Document Type and Number:
Japanese Patent JP3703507
Kind Code:
B2
Abstract:
PURPOSE: To use a nonvolatile memory without revising address specification to it by providing first, second memories, an address table and an address translation logic circuit converting an external address when operation is impossible.
CONSTITUTION: The address translation logic circuit 61 checks conditional information in the address table 62, and recognizes the number of defective blocks of a block address or below of a specified card address in a memory array 11. Then, the circuit 61 adds the block address to the number to apply it to the block with different converted block address. Then, the circuit 61 checks the table 62 to decide whether or not the converted block address is applied to a defective block yet. When the converted block address is applied to the final block of a flash EPROM, the circuit 61 increases the converted block address to make it the adjacent indefective block of the next memory.
Inventors:
David M Brown
Application Number:
JP15552794A
Publication Date:
October 05, 2005
Filing Date:
June 15, 1994
Export Citation:
Assignee:
INTEL CORPORATION
International Classes:
G06F12/16; G06F12/00; G06F12/06; G06K19/073; G11C16/02; G11C29/00; G11C29/04; (IPC1-7): G11C29/00; G06F12/06; G11C16/02
Domestic Patent References:
| JP4123398A | ||||
| JP56037897A | ||||
| JP5046490A | ||||
| JP2226446A | ||||
| JP63211448A |
Attorney, Agent or Firm:
Masaki Yamakawa
Hiroro Kurokawa
Masayuki Konno
Osamu Nishiyama
Shigeki Yamakawa
Hiroro Kurokawa
Masayuki Konno
Osamu Nishiyama
Shigeki Yamakawa
Previous Patent: DRAG BRAKING METHOD OF POLYPHASE DC MOTOR AND CIRCUITRY
Next Patent: DEVICE FOR DETECTING AND CORRECTING PICTURE TRANSFER SMEAR
Next Patent: DEVICE FOR DETECTING AND CORRECTING PICTURE TRANSFER SMEAR