To improve power consumption by reducing current flowing a bit line when reading is performed and to avoid operation defect due to concentration of charged/discharged current.

A memory cell array 1 has a hierarchical structure where bit lines BL are split from a main data line MDL and an inverting sense circuit 10 is inserted between the main data line MDL and the bit lines BL. The inverting sense circuit 10 senses data of the bit lines BL when reading the data and sets so that current does not flow in either the main data line MDL on the upper layer side or the bit line BL on the lower layer side when the current flows in the other. Thus, parasitic capacitance of the bit line reduces, power consumption when reading is reduced, parasitic capacitance for charging/discharging in the case of data "1" and parasitic capacitance for charging/discharging in the case of data "0" are flattened, peak of the current is offset, and unevenness in peak current decreases.