NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND DEPLETION TYPE MOS TRANSISTOR

Japanese Patent JP2011009695

A

To provide a nonvolatile semiconductor memory device and a depletion type MOS transistor, which improve a breakdown voltage of a transistor and improve operation reliability.

The transistor is equipped with: a gate electrode 26; a channel region 22 having a first impurity concentration; a source and drain diffusion region 21 having a second impurity concentration higher than the first impurity concentration; an overlapping region 24 which is formed in a region where the channel region 22 overlaps the source and drain diffusion region 21 and has a third impurity concentration higher than the second impurity concentration region; a contact region 23 having a fourth impurity concentration higher than the second impurity concentration; and an impurity diffusion region 27 which is formed inside a part of the source and drain diffusion region 21 and has a fifth impurity concentration higher than the second impurity concentration and lower than the fourth impurity concentration. The impurity diffusion region 27 is in contact with the contact region 23 and away from the overlapping region 24.

KUTSUKAKE HIROYUKI
GOMIKAWA KENJI
KATO TOKO
NOGUCHI MITSUHIRO
ENDO MASATO

JP2010029218A

January 13, 2011

February 12, 2010

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TOSHIBA CORP

H01L27/115; H01L21/768; H01L21/8247; H01L27/10; H01L29/78; H01L29/788; H01L29/792

Kurata Masatoshi
Satoshi Kono
Makoto Nakamura
Yoshihiro Fukuhara
Takashi Mine
Toshio Shirane
Sadao Muramatsu
Nobuhisa Nogawa
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Katsumura Hiro
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori
Takuzo Ichihara
Yamashita Gen

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