To securely read data at a high speed in a nonvolatile semiconductor memory device having a non-conductive trap gate.

Source/drain regions of cell transistor Mi and an adjacent cell transistor Mi-1 or Mi+1 are electrically connected in common by a column line SDLi or SDLi+1. Column selecting means (P/B1-P/B9)apply reference voltage (0V) to a selected column line, and set read-out voltage states (BL) to the other column lines. Data D of a plurality of bits are read simultaneously from a plurality of column lines being adjacent the column line to which the reference voltage (0V) is applied, but, at the time, since a current is not made to flow in a cell transistor (e.g. M3, M7) not to be read and not connected to the column line to which the reference voltage (0V) is applied, the data D can be surely read at high speed.