To provide a split-gate nonvolatile semiconductor memory device capable of performing fast erasing operation by decreasing the coupling capacity between an erasing gate and a floating gate, and to provide a method of manufacturing the nonvolatile semiconductor memory device.

The nonvolatile semiconductor memory device includes: a floating gate 20; an erasing gate 40; and a control gate. The floating gate 20 is provided on a channel region of a semiconductor substrate 10 through a first insulating layer 12. The erasing gate 40 is provided on the floating gate 20 through second insulating layers 13 and 14. The control gate is provided beside the floating gate 20 and the erasing gate 40 through a third insulating layer. The floating gate is U-shaped, so that the floating gate 20 can be opposed to the erasing gate 40 at an end having extremely small area through the second insulating layer 14. Consequently, the coupling capacity between the floating gate 20 and the erasing gate 40 can be made small to suppress an erasing voltage in erasing operation small.