To provide an electrically rewritable nonvolatile semiconductor memory device which features low power consumption, high speed operation, and reduced effective cell area.
This electrically rewritable nonvolatile semiconductor memory device has a memory cell array in which a plurality of memory cells are arranged in a matrix form of rows and columns, wherein each memory cell comprises a MOSFET having a floating gate electrode 3. In write operation, a positive voltage is applied to an n-type drain region 7 and a negative voltage is applied to a control gate 5, while a source region 6 is grounded. In erase operation, a positive voltage is applied to the control gate 5, while all the other electrodes and the semiconductor substrate 1 are grounded. The write and erase operations utilizing a tunnel phenomenon suppress the power consumption. Since the drain voltage in the write operation can be low while applying a negative voltage to the word line, degradation of the gate oxide film in the channel part in the rewrite operation can be relaxed.
ADACHI TETSUO
TANAKA TOSHIHIRO
SASAKI TOSHIO
KUME HITOSHI
