To provide a highly reliable nonvolatile semiconductor memory device capable of preventing the occurrence of latch-up.

A floating gate type electric field effect transistor Tr connected to a word line and a bit line is arranged on a memory cell array in the form of a matrix. The floating gate type electric field effect transistor Tr has a source 13 and a drain 14 formed in a P type well provided in the N type well of a P type semiconductor board 10, a floating gate 16 formed through a tunnel oxidation film 15 between the sources 13 and the drains 14, and a control gate 18 formed through an interlayer insulation film 17 on the floating gate 16. When an elimination pulse is applied, 6 V is applied on a P type well 12 by using a first high voltage pump circuit 1, and 9 V is applied on an N type well 11 by using a second high voltage pump circuit 2.