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Title:
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JP2011171475
Kind Code:
A
Abstract:

To provide a nonvolatile semiconductor memory device that can avoid failure by alleviating an electric field impressed to an inter-gate insulating film of a dummy cell.

The nonvolatile semiconductor memory device has a first conductive well 102, a first element isolation film 121 formed in the well, a second element isolation film 122 formed parallel to the first element isolation film and the width of whose substrate surface up to the first element isolation film is set to be wide, a memory cell 201 containing a gate insulating film, floating gate, inter-gate insulating film, and control gate formed in sequence in the first element isolation film, a dummy cell 301 containing a gate insulating film, floating gate, inter-gate insulating film, and control gate formed in turn between the first and second element isolation films, and a second conductive diffusion layer 103 formed below the dummy cell and in the well between the first and second element isolation films and having its upper surface at a position higher than the bottom surface of the element isolation film.


Inventors:
NARUGE KIYOMI
Application Number:
JP2010000033291
Publication Date:
September 01, 2011
Filing Date:
February 18, 2010
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Attorney, Agent or Firm:
勝沼 宏仁
佐藤 泰和
川崎 康
関根 毅
赤岡 明
山ノ井 傑