Title:
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JP2019161056
Kind Code:
A
Abstract:
To reduce a writing voltage.SOLUTION: A nonvolatile semiconductor memory device includes: a semiconductor substrate; a first wiring layer 10 provided to an upper direction of the semiconductor substrate, and extended to a first direction; a plurality of second wiring layers 14 provided to the upper direction of the first wiring layer 10, extended to a second direction crossing to the first direction, and arranged along a third direction crossing to the first and second directions, and vertical to a semiconductor substrate; a semiconductor layer 11 extended along the third direction, and electrically connected to the first wiring layer 10; a first insulation layer 12 extended along the third direction, and provided between the semiconductor layer 11 and the plurality of second wiring layers 14; and a plurality of first oxidation layers 23 in which a resistance value is changed by contacting one to the plurality of second wiring layers, contacting the other one to the first insulation layer 12, and applying a voltage to the plurality of second wiring layers.SELECTED DRAWING: Figure 3
Inventors:
SUZUKI KUNIFUMI
YAMAMOTO KAZUHIKO
YAMAMOTO KAZUHIKO
Application Number:
JP2018046905A
Publication Date:
September 19, 2019
Filing Date:
March 14, 2018
Export Citation:
Assignee:
TOSHIBA MEMORY CORP
International Classes:
H01L21/8239; G11C16/04; G11C16/08; H01L21/336; H01L27/105; H01L29/788; H01L29/792; H01L45/00; H01L49/00
Attorney, Agent or Firm:
Kurata Masatoshi
Nobuhisa Nogawa
Takashi Mine
Naoki Kono
Ukai Ken
Nobuhisa Nogawa
Takashi Mine
Naoki Kono
Ukai Ken