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Patent Searching and Data


Title:
NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT
Document Type and Number:
Japanese Patent JPS6055669
Kind Code:
A
Abstract:

PURPOSE: To enable write/erase at high speed with low voltage by a method wherein the first and second Si nitride films are arranged on an Si substrate or the first Si region, and an Si oxide film on the upper layer of the second Si nitride film into a structure of three-layer insulation films.

CONSTITUTION: At least part of an insulation structural region 10 under a conductive electrode 7 is put in the structure of three-layer insulation films, from the surface 1 of the first Si region 1, in the order of the first Si oxide-nitride films or Si nitride film 31 produced by direct nitriding the second Si nitride film 32 produced by CVD, and an Si oxide film 8 produced by thermal oxidation. Since the memory characteristic is determined by trapping in the neighborhood of the interface between the oxide film 8 on the nitride film 32 and the film 32, the speed-up and reduction in voltage of write/erase not possessed by the conventional MNOS element, and the lamination of the region 10 can be realized by the method as above.


Inventors:
HAYASHI YUTAKA
SUZUKI HIDEKAZU
Application Number:
JP16347083A
Publication Date:
March 30, 1985
Filing Date:
September 06, 1983
Export Citation:
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Assignee:
KOGYO GIJUTSUIN
International Classes:
H01L21/8247; H01L29/788; H01L29/792; (IPC1-7): H01L29/78
Attorney, Agent or Firm:
Director, Electronic Technology Research Institute, AIST