PURPOSE: To perform miniaturization, integration of a memory cell and to electrically erase data in the operation by providing first, second diffused layers formed in a semiconductor substrate, specific first gate electrode, second insulating film, second gate electrode and third gate electrode.

CONSTITUTION: First, second diffused layers 2, 3 formed in a first conductivity type semiconductor substrate 1, a first gate electrode 6 formed on part of a channel region 4 existing between the layers 2 and 3 and on the layer 2 through an insulating film 5, second insulating films 8a, 8b formed at both sides of the electrode 6 and formed by extending to the substrate 1, a second gate electrode 9a formed on a channel region 4 and on the film 8a existing on one side of the electrode 6, and a third gate electrode 9b formed on the layer 2 and on the film 8b existing on the other side of the electrode 6 are provided.