Title:
不揮発性半導体記憶装置およびその製造方法
Document Type and Number:
Japanese Patent JP4526587
Kind Code:
B2
Abstract:
A nonvolatile semiconductor memory apparatus 25 comprises a semiconductor substrate 11, a lower-layer wire 12 formed on the semiconductor substrate 11, an upper-layer wire 20 formed above the lower-layer wire 12 to cross the lower-layer wire 12, an interlayer insulating film 13 provided between the lower-layer wire 12 and the upper-layer wire 20, and a resistance variable layer 15 which is embedded in a contact hole 14 formed in the interlayer insulating film 13 and is electrically connected to the lower-layer wire 12 and the upper-layer wire 20. The upper-layer wire 20 includes at least two layers which are a lowermost layer 21 made of an electrically-conductive material having a hydrogen barrier property and an electric conductor layer 22 having a specific resistance which is lower than a specific resistance of the lowermost layer 21.
Inventors:
Takumi Mikawa
Tsuyoshi Takagi
Tsuyoshi Takagi
Application Number:
JP2008526736A
Publication Date:
August 18, 2010
Filing Date:
July 18, 2007
Export Citation:
Assignee:
Panasonic Corporation
International Classes:
H01L27/10; G11C13/00; H01L45/00; H01L49/00
Domestic Patent References:
| JP2005203733A | 2005-07-28 | |||
| JP2006120707A | 2006-05-11 | |||
| JP2006121044A | 2006-05-11 | |||
| JP2004327658A | 2004-11-18 | |||
| JP2004158852A | 2004-06-03 | |||
| JP2004303996A | 2004-10-28 | |||
| JP2006514440A | 2006-04-27 | |||
| JPH09293869A | 1997-11-11 |
Attorney, Agent or Firm:
Patent business corporation Yuko patent office