To obtain a nonvolatile semiconductor memory in which a third positive potential for an erasure verify operation can be supplied from a negative- voltage generation circuit which supplies a negative voltage or a ground voltage to a word line.

In an EEPROM, a P-potential supply circuit 201 which supplies a potential to the source of a P-channel transistor 101 constituting an inverter 103 connected to a word line W511 from a word line W000 is provided, an N-potential supply circuit 202 which supplies a potential to the source of an N-channel transistor 102 constituting the inverter 103 is provided, a read-write judgment circuit 209 which judges whether an operation is performed in a readout mode or a write mode is provided, and an erasure judgment circuit 109 which judges whether an operation is performed in an erasure mode or not is provided. On the basis of the output of the read-write judgment circuit 209 and on the basis of the output of the erasure judgment circuit 109, the P- potential supply circuit 201 outputs any one of a first positive potential, a second positive potential and a ground potential, and the N-potential supply circuit 202 outputs any one of a third positive potential, the ground potential and a negative potential.