PURPOSE: To enable layout even if a word line pitch is short, by connecting the first bit line to the second bit line through MOS transistors, by connecting word lines to the second low decorder, and by connecting the output of the second low decorder to a plurality of word lines in common.
CONSTITUTION: A bit line is composed of the first bit line 30 and second bit line 31, the drains of memory transistors are connected to the first bit line 30, the bit line 30 is connected to the second bit line 31 through MOS transistors (T1-T4), and the output of the first low decorder 32 is put into the gates of the MOS transistors. The bit line 31 is connected to a write circuit 12 and a sense amplifier 13 through a Y gate 8, and the output of the second low decorder or word lines are connected in common by a plurality. Accordingly, the size of memory cells can be reduced, and it becomes possible to lay out low decorders even if the word line pitch is short.
MIYAWAKI YOSHIKAZU
NAKAYAMA TAKESHI
KOBAYASHI SHINICHI
HAYASHIGOE MASANORI
| JPH0314272A | 1991-01-22 | |||
| JPS63225998A | 1988-09-20 | |||
| JPS6069892A | 1985-04-20 | |||
| JPS63226060A | 1988-09-20 |