PURPOSE: To permit high speed memory by setting negative electric potential to a substrate composing of memory at a lower value than a barrier level at the interface between the substrate and a gate insulating film wherein the storage of electrons at the trapping center in the gate insulating film is prevented.
CONSTITUTION: An n+ type source region 2 and an n+ type drain region 3 are formed by diffusion on a p type Si substrate 1. And an SiO2 gate insulating film 4 having charge trapping center is formed on the substrate 1 exposed between the source region 2 and the drain region 3. A poly-crystalline Si gate electrode 5 is instlled on the SiO2 gate insulating film 4 to form a floating gate-type nonvolatile memory. In this composition, negative electric potential to the substrate 1 is selected at a lower value than a barrier level at the interface between the substrate 1 and the film 4. Namely, when the electric potential to the electrode 5 is VG, electric potential shown in a formula [I] is given to the substrate 1. Where: q is the quantity of electricity, so is a barrier level, tox is film 4 thickness. In this way, a threshold voltage will not fluctuate.
IWAHASHI HIROSHI
ASANO MASAMICHI
| JPS495274A | 1974-01-17 |