Title:
NONVOLATILE STORAGE AND ITS VERIFICATION METHOD
Document Type and Number:
Japanese Patent JPH01279499
Kind Code:
A
Abstract:
PURPOSE: To attain margin guarantee of a write state at verification by increasing an equivalent resistance of a part converting a current flowing to a memory in a readout circuit into a voltage.
CONSTITUTION: With a signal Vin applied to a gate of a p-channel MOSFET 3, the voltage is 0V in the normal readout mode and reaches an intermediate voltage between 0V and Vcc-Vthp (Vthp is a threshold value of the FET 3) in the verify mode. The potential of a node A is decreased by increasing the voltage Vin resulting in increasing the equivalent resistance. If the voltage of the node A is high, the output of the inverter of the next stage goes to L and the written memory is read correctly.
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Inventors:
SEKI KOICHI
Application Number:
JP10899188A
Publication Date:
November 09, 1989
Filing Date:
May 06, 1988
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G11C17/00; G11C16/02; G11C16/06; H01L21/822; H01L21/8247; H01L27/04; H01L27/10; H01L29/78; H01L29/788; H01L29/792; (IPC1-7): G11C17/00; H01L27/04; H01L27/10; H01L29/78
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)