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Title:
NONVORATILE SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JPS5987697
Kind Code:
A
Abstract:

PURPOSE: To prevent current that flows in a memory cell from becoming above a specified value at the time of data writing even when effective channel length of each memory cell becomes short by inserting a part between drain and source of an MOS transistor between a common source connecting point of plural memory cells and a reference potential point.

CONSTITUTION: Current that flows in an MOS transistor 31 does not become above IO. This is because current that flows in the MOS transistor becomes saturation at a value when gate bias voltage is constant. Accordingly, if this saturated current value IO is prescribed as a maximum current value that can be flown in a memory cell 24 by design of channel width, channel length etc. of the MOS transistor 31, current above this value does not flow in the memory cell 24 in which data are being written. When the value of current that flows in the memory 24 is going to exceed IO, voltage of a circuit point 25 rises, and increase of current is obstructed.


Inventors:
TANAKA SUMIO
ATSUMI SHIGERU
Application Number:
JP19711082A
Publication Date:
May 21, 1984
Filing Date:
November 10, 1982
Export Citation:
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Assignee:
TOSHIBA KK
International Classes:
G11C16/06; G11C17/00; H01L21/8247; H01L29/788; H01L29/792; (IPC1-7): H01L29/78
Attorney, Agent or Firm:
Takehiko Suzue