Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
NORMALITY TESTING METHOD OF NEW TIME SIGNAL GUIDE DEVICE AND NORMALITY TESTING DEVICE USED THEREFOR
Document Type and Number:
Japanese Patent JP2001289973
Kind Code:
A
Abstract:

To provide a normality testing method and a normality testing device capable of easily confirming a phase error and the stepping state of a built-in clock of a new time signal guide device to Japan Standard Time.

When a maintenance terminal is not connected to the new time signal guide device 1, the phase error of a one sec TAE pulse synchronized with the time of the built-in clock outputted from a first output terminal 12a of a serial connector 12 and a one sec GPS pulse received by a GPS receiver 8 via a GPS antenna 6 is measured by a phase comparing circuit 9 of a phase error tester 7 to be displayed on a display part 10, and when the maintenance terminal is not connected to the new time signal guide device 1 serial time information on the built-in clock outputted from a second output terminal 12b of the serial connector 12 is introduced to a personal computer 15 of a time confirming communication terminal 4, and the serial time information and information on the Japanese Standard Time are displayed in parallel on a display device to confirm the stepping state of the built-in clock.


Inventors:
OHARA TOSHIO
ARIMURA TOSHIHIKO
Application Number:
JP2000108956A
Publication Date:
October 19, 2001
Filing Date:
April 11, 2000
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
FUJITSU I NETWORK SYSTEMS LTD
International Classes:
G04D7/00; G04G5/00; G04G9/00; G04R20/00; G04R20/02; G04R20/08; (IPC1-7): G04D7/00; G04C9/02; G04G5/00; G04G9/00
Attorney, Agent or Firm:
Akihide Sugimura (2 outside)