Title:
NOVEL SHAPE LEAD TYPE SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS5994860
Kind Code:
A
Abstract:
PURPOSE: To reduce the outer dimension of a package for sealing a semiconductor chip by a method wherein a plurality of leads are arranged in non-parallel state with one another along the side surface of the package, and tips of leads are arranged in parallel state with one another.
CONSTITUTION: Intervals among lead parts 7, 7', and 7" led out from a sealed outer form 5' are different respectively, and are different from intervals among outer lead parts 2, 2', and 2". The intervals among the outer lead parts 2, 2', 2" are at constant pitches. Thus, the outer dimension of the package can be made small, which becomes advantageous in respect to mounting on a printed substrate.
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Inventors:
BONSHIHARA MANABU
Application Number:
JP20475482A
Publication Date:
May 31, 1984
Filing Date:
November 22, 1982
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
H01L23/50; H01L23/495; H05K3/30; (IPC1-7): H01L23/48
Domestic Patent References:
| JPS481859A |
Attorney, Agent or Firm:
Uchihara Shin