Title:
NVRAM USING HIGH-VOLTAGE TFT DEVICES
Document Type and Number:
Japanese Patent JP3208383
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide an NVRAM that is integrated with good space efficiency and good process efficiency by forming a non-volatile semiconductor memory cell on a surface of a substrate or on a semiconductor layer, and forming complementary thin film transistors that are connected to a control gate of a non- volatile semiconductor memory cell.
SOLUTION: An integrated structure 10 includes p+ doped semiconductor layers 11. Lightly doped p- layers 12 are formed to produce active devices. On layers 12, complementary CMOS transistors consisting of a pFET 20 and an nFET 30, transistors of a complementary high-voltage driver consisting of a HVPFET 40 and a HVNFET 50, and an NVRAM cell 60 are formed. With these structures, thickness of layer 12 can be optimized depending on the depth of an n-well 21.
Inventors:
Terence B. Hook
James S. Nacos
Richard Kew Williams
James S. Nacos
Richard Kew Williams
Application Number:
JP7773499A
Publication Date:
September 10, 2001
Filing Date:
March 23, 1999
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
H01L21/8247; H01L21/762; H01L27/10; H01L27/105; H01L27/115; H01L29/786; H01L29/788; H01L29/792; (IPC1-7): H01L21/8247; H01L21/762; H01L27/10; H01L27/115; H01L29/786; H01L29/788; H01L29/792
Domestic Patent References:
| JP7226490A | ||||
| JP62213272A | ||||
| JP3129765A | ||||
| JP7321327A | ||||
| JP9199688A |
Attorney, Agent or Firm:
Hiroshi Sakaguchi (1 person outside)