PURPOSE: To obtain a more stable and uncomplicated memory device by connecting a signal detecting device to a bit line and isolating the bit line from the device in a part of a device setting period.

CONSTITUTION: A memory cell is arranged in a single array 23 and connected to one sense amplifier bank, with bit lines BL5 and BL6 terminating before reaching the other bank. A reference voltage circuit 21 is arranged between the bit line terminating end and the sense amplifier bank 22. A switching insulating transistor T5 is provided between the bit line BL and the related sense amplifier 22, with the bit line BL5 and a cut reference line RVL each directly connected to a sense amplifier 22 together with the FET 6 of the reference voltage circuit 21, at the time of an active state. With this structure, the bit line is separated from the device during the period of device setting, so that a stable memory device is obtained.