To obtain a high-speed O/S (open or short-circuiting) test circuit, and at the same time the O/S test circuit that can be designed in an area array IC by connecting a plurality of signal traces to a discharge signal line via a third switching device under testing.

A circuit has four capacitors C0-C3, and tests a plurality of signal traces chnl-0-chnl-N. With one test, switches SA0-SA3, SB0-SB3, and SC0-SCN select one capacitor for feeding an electric charge to a signal trace that is selected as a result. The circuit has two operation modes. In a test mode, the capacitance of each signal trace is measured. Then, a signal that is obtained by digitizing the equilibrium voltage of the capacitor C1 and the signal trace chnl-91 is stored in a memory block sram 203 through an amplifier block LAmp 201 and an A/D block 202. In a read mode, the stored data is read by a signal-processing sub-system.