To provide an operating mode setting circuit for surely setting a test mode of various kinds, even when a manual evaluation tool is used.

A logic circuit 11 is reset by a system reset signal SRST, while resetting FFs 17 and 18 and a counter 20 by a test reset signal TRST. Then, resetting is removed of the FFs 17 and 18 and of the counter 20 with the logic circuit 11 being left, as it is. Each time a test-setting signal TRST is switched between "H" and "L", an enable signal of "H" is given from an EOR 19 to the counter 20 to count the counting value CN, in synchronization with the internal clock CKI. The counting value CN is decoded by a decoder 21 and given as a mode setting signal to the logic circuit 11. When the reset signal SRST is released, after setting the prescribed counting value CN, the logic circuit 11 starts operation in an operating mode that corresponds to the mode-setting signal.