OPERATING TECHNIQUE FOR REDUCING EFFECT OF COUPLING BETWEEN STORAGE ELEMENTS OF NONVOLATILE MEMORY OPERATED IN MULTIPLE DATA STATES

Title:

OPERATING TECHNIQUE FOR REDUCING EFFECT OF COUPLING BETWEEN STORAGE ELEMENTS OF NONVOLATILE MEMORY OPERATED IN MULTIPLE DATA STATES

Document Type and Number:

Japanese Patent JP2003109386

Kind Code:

A

Abstract:

To minimize the effect of charge coupling between adjacent floating gates and to compress the distribution.

A flash electrically erasable and programmable ROM (EEPROM) in which storage elements are electrically floating gates is operated so that the effect of charge coupled between adjacent floating gates is minimized by programming again one part of cells after programming of adjacent cells. Also, second programming operation compacts the distribution for a charge level within at least some of the programming states. This increases the separation between states and allows more states to be included within a given storage window.

Inventors:

CHEN JIAN
TANAKA TOMOHARU
FONG YUPIN
QUADER KHANDKER N

Application Number:

JP2002187020A

Publication Date:

April 11, 2003

Filing Date:

June 27, 2002

Export Citation:

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Assignee:

SANDISK CORP
TOSHIBA CORP

International Classes:

G11C16/02; G11C11/56; G11C16/00; G11C16/04; G11C16/12; G11C16/34; H01L21/8247; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): G11C16/02; G11C16/04; H01L21/8247; H01L27/115; H01L29/788; H01L29/792

Attorney, Agent or Firm:

Meisei International Patent Office

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