Title:
OPERATION CIRCUIT
Document Type and Number:
Japanese Patent JPS63113757
Kind Code:
A
Abstract:
PURPOSE:To execute both an operation in sum of products and an operation in polynomial at high speed by providing two selection circuits which select inputs from an accumulator register and output them. CONSTITUTION:A coefficient an is inputted from a first input terminal 1 and a constant (x) is inputted from a second input terminal 2. A first selection circuit 3 selects the input an from the first input terminal 1 and inputs it in a multiplication circuit 4. Next, the coefficient an-1 is inputted from the first input terminal 1 and a second selection circuit 5 selects the input an-1 from the first input terminal 1 and inputs it in an addition circuit 6. The addition circuit 6 adds the input an-1 to the output anx from the multiplication circuit 4 and the added result anx+an-1 is accumulated in the accumulator register 7. And the first selection circuit 3 selects the output from the accumulator register 7 and inputs it in the multiplication circuit 4. Meanwhile, an-2 is inputted from the first input terminal 1 and the second selection circuit 5 selects the input an-2 from the first input terminal 1 and inputs it the addition circuit 6. And then an-2 and (anx+an-1)x are added and the added result (anx+an-1)x+ an-2) is accumulated in the accumulator register 7.
Inventors:
KURODA ICHIRO
Application Number:
JP25838886A
Publication Date:
May 18, 1988
Filing Date:
October 31, 1986
Export Citation:
Assignee:
NEC CORP
International Classes:
H03H17/02; G06F17/10; H03H17/00; (IPC1-7): G06F15/31; H03H17/00
Attorney, Agent or Firm:
Yoshiyuki Iwasa