PURPOSE: To enable the discovery of troubles of a counter beforehand by releasing an action command input of a counter with an AND taken between the input and a signal detecting the counter which has reached the final integrated value.

CONSTITUTION: When an action command B fails to be input, a binary counter 10 is set for data corresponding to the final integrated value. When the action command B is given, the memory contents of the address corresponding to the final integrated value of the counter 10 is output from a fixed memory 14. Thereafter, the counter 10 adds up speed pulses A. Output data of the fixed memory 14 are provided to a comparator 17 through a frequency conversion circuit 15. In the normal operation, an AND circit 16 connected to the output of the fixed memory 14 always outputs a signal I to release the action command B. If the action command B fails to be released after the set time of a timer 18 passes, a brake command is outputted.