PURPOSE: To realize an operation control of pipeline register system capable of simple control and at the same time reducing the number of devices, by constituting the system to prefetch the instruction of branch address to a register before execution of a branch instruction.

CONSTITUTION: The macroinstruction to be used by a user and its accessary data are stored in the macroinstruction memory 81. The macroinstruction or data stored in the address set to the address register 83 is fetched to the fetch register 87 via the memory data bus 85 and furthermore to the executing register 91 via the change- over switch 89. The 1st decoder 93 checks whether the supplied macroinstruction is an ML instruction or not. After the contents of register 91 is processed by the ALU, the contents of register 87 is shifted to the register 91 and then decoded by the 2nd decoder 95. Thus in case a decision instruction is processed through the ALU, the instruction of branch address is prepared in the instruction registers 125 and 127. At the same time, the instruction of return address is prepared in advance at the instruction register stack 129.