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Title:
OPERATIONAL AMPLIFIER AND LINE TERMINATING DEVICE
Document Type and Number:
Japanese Patent JPH05191162
Kind Code:
A
Abstract:

PURPOSE: To provide a class 'AB' amplifier which has stable power consump tion and characteristic and has a high driving capability with a low power consumption by driving respective output MOSFETs in a push-pull output stage by low-gain prebuffers respectively.

CONSTITUTION: A folded cascode differential amplifier is used in an input stage 1. Prebuffers consisting of a differential amplification means 2a of PMOS input and a differential amplication stage 2b of NMOS input are provided as level shifters in the succeeding stage. Resistances are inserted between drain terminals of load MOSFETs Q23 and Q24 and load MOSFETs Q28 and Q29 which are connected as current mirrors in prebuffers 2a and 2b to suppress the gains of prebuffers 2a and 2b to about 10dB or lower. Output MOSFETs Q31 and Q32 in a push-pull output stage 3 are driven by low-gain prebuffers 2a and 2b. Consequently, the circuit which has a high tolerance to the dependency on various parameters for mass production is obtained, and the power consumption and the characteristic are stabilized, and a high driving capability is obtained with a low power consumption.


Inventors:
TOMATSU TAKASHI
NODA TAKAAKI
Application Number:
JP21275392A
Publication Date:
July 30, 1993
Filing Date:
August 10, 1992
Export Citation:
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Assignee:
HITACHI LTD
AKITA DENSHI KK
International Classes:
H03F3/30; H03F3/345; H03F3/45; H04L25/02; (IPC1-7): H03F3/30; H03F3/345; H03F3/45
Attorney, Agent or Firm:
Tomio Ohinata



 
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