Title:
OPERATIONAL AMPLIFIER
Document Type and Number:
Japanese Patent JP3119221
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To balance a phase inverting input transistor(TR) and a phase inverting output TR, even if a common mode input range of an input stage is decreased toward a GND level.
SOLUTION: An N-channel non-doped MOS TR is adopted respectively for a phase inverting input TR MND 4 and a phase inverting output TR MND 5, then a threshold of the phase inverting input TR MND 4 between sufficiently lower than an output voltage of an input stage at a node N1. As a result, the phase inverting input TR MND 4 and the phase inverting output TR MND 5 are kept balanced.
Inventors:
Tsuneki Sasaki
Application Number:
JP31687697A
Publication Date:
December 18, 2000
Filing Date:
November 18, 1997
Export Citation:
Assignee:
NEC
International Classes:
H03F3/45; (IPC1-7): H03F3/45
Domestic Patent References:
| JP4217106A | ||||
| JP5981909A | ||||
| JP6372206A |
Attorney, Agent or Firm:
Kaneyuki Matsuura
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