Title:
OPTICAL ELEMENT PACKAGING SUBSTRATE AND HYBRID OPTICAL INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3716951
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To lower the floating capacity of optical element mounting sections, to assure fixing strength and to facilitate the mounting of plural optical elements by setting the height of first solder pattern surfaces on the surfaces of terrace parts higher than the height of the surfaces of second solder patterns on electrode parts.
SOLUTION: The optical element mounting section 23 parts have the terrace parts (silicon terrace parts) 1a provided with projecting parts having flat front surfaces and recessed parts (electrode parts) 1b formed to be made lower than the front surfaces of the terrace parts 1a. Further, first ground surface metallic patterns and the first solder patterns 14 are successively laminated atop the terrace parts 1a. The surfaces of the electrode parts 1b include insulating film layers partly formed with apertures and these apertures and are formed with the electrode patterns successively laminated with such second ground surface metallic patterns to cover the wider regions and such solder patterns as to cover the wider regions. The height of the surfaces of the first solder patterns 14 on the terrace parts 1a is set higher than the height of the second solder pattern surfaces on the electrode parts 1b.
Inventors:
Takaharu Oyama
Yuji Akahori
Yasufumi Yamada
Shinji Mino
Yuji Akahori
Yasufumi Yamada
Shinji Mino
Application Number:
JP28554896A
Publication Date:
November 16, 2005
Filing Date:
October 28, 1996
Export Citation:
Assignee:
Nippon Telegraph and Telephone Corporation
International Classes:
G02B6/13; G02B6/122; (IPC1-7): G02B6/13
Domestic Patent References:
| JP8078657A | ||||
| JP7193098A | ||||
| JP7235566A | ||||
| JP8036121A | ||||
| JP6275870A | ||||
| JP7193535A | ||||
| JP3171643A |
Attorney, Agent or Firm:
Yoshikazu Tani
Kazuo Abe
Kazuo Abe