Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
MRAMの性能を向上させるための最適な書込導体レイアウト
Document Type and Number:
Japanese Patent JP5100935
Kind Code:
B2
Abstract:
An optimal write conductor layout structure for improved MRAM performance is disclosed. A write conductor layout structure (10) for a magnetic memory cell includes a data storage layer (20) having a first layer width (WD1) in a first direction (V) and a second layer width (WD2) in a second direction (H). The data storage layer (20) is positioned between a first conductor (30) having a first width (WC1) in the first direction (V) and a second conductor (320 having a second width (WC2) in the second direction (H). The first and second conductors (30, 32) cross the data storage layer (20) in the first and second direction (V, H) respectively. The first width (WC1) of the first conductor (30) is less than the first layer width (WD1) of the data storage layer (20) and the first width (WC1) of the first conductor (30) is positioned so that the first layer width (WD1) overlaps the entirety of the first width (WC1) of the first conductor (30). The second width (WC2) of the second conductor (32) is less than the second layer width (WD2) of the data storage layer (20) and the second width (WC2) of the second conductor (32) is positioned so that the second layer width (WD2) overlaps the entirety of the second width (WC2) of the second conductor (32). The narrow widths of the first and second conductors (30, 32) eliminates misalignment between the conductors (30, 32) and the data storage layer (20), reduces leakage of a write magnetic field (HX, HY) generated by currents (IY, IX) applied to the first and second conductors (30, 32), and can generate the write magnetic field (HX, HY) with less current thereby reducing power consumption in the memory cell.

Inventors:
Manoi Batacharya
Thomas Anthony
Application Number:
JP2001221215A
Publication Date:
December 19, 2012
Filing Date:
July 23, 2001
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
G11C11/14; H01L21/8246; G11C11/15; G11C11/16; H01L27/105; H01L27/22; H01L43/08
Domestic Patent References:
JP11345485A
JP11273336A
JP9293373A
JP2001196658A
JP2001519582A
JP6243673A
JP9293373A
Foreign References:
WO2000007191A1
WO1999018578A1
Attorney, Agent or Firm:
Hatta International Patent Corporation