To produce a binary adder of two stages of gates.

Starting point two digits s, s+1 digit AB=NAND (1) digit upper signals C, L (0 volt) are put in AND, Pts (2) to make the output L to emit laser diode LD, Uc (5) light, 00 of an intermediate digit and an L signal are put in Pts to make Pts output high to turn off the light of Uc (5), NAND, Qts (6) output are made H by the same digit upper signals C and L to prevent LD, Zc from emitting light, and Qts output is made L by an L signal to allow Zc to emit light. When AB=11 or 00, AND, GO output are made L to make LD, Ug to emit light and when AB=10 or 01, NAND, G1 output are made low to make LD, Zg to emit light. When both of Ug and Uc emit light, two photodiodes FD are continued to output H signal to output 11+1=1, 00+1=1 and when both of Zc and Zg emit light, two FD are continued to output H signal to output 10+0=1, 01+0=1, in this optoelect 00 cut adder.