Title:
ORTHOGONAL ARITHMETIC UNIT
Document Type and Number:
Japanese Patent JP3697733
Kind Code:
B2
Abstract:
PURPOSE: To unnecessitate the addition of a butterfly circuit by adding a function performing a butterfly calculation of the DCT arithmetic result corresponding to two fields to the post-butterfly circuit of a second stage circuit.
CONSTITUTION: A first stage circuit 1 is composed of a pre-butterfly circuit 12, a DCT circuit 13 and a post-butterfly circuit 14, etc. A second stage circuit 2 is composed of a pre-butterfly circuit 22, a DCT circuit 23 and a post-butterfly circuit 24, etc. The pre-butterfly circuit 12 of the first stage circuit 1 is used for performing the butterfly calculation for returning the DCT arithmetic result of two fields for which the butterfly calculation is performed to the DCT arithmetic result for every field in a field inverse DCT. The post-butterfly circuit 24 of the second stage circuit 2 is used for performing the butterfly calculation of the DCT arithmetic result corresponding to two fields in a field forward DCT.
Inventors:
Toru Wakaki
Application Number:
JP33013894A
Publication Date:
September 21, 2005
Filing Date:
December 06, 1994
Export Citation:
Assignee:
ソニー株式会社
International Classes:
H04N19/60; G06F17/14; H03M7/30; H04N19/119; H04N19/137; H04N19/172; H04N19/196; H04N19/42; H04N19/423; H04N19/625; (IPC1-7): G06F17/14; H04N7/30
Domestic Patent References:
| JP5153403A | ||||
| JP5145763A |
Attorney, Agent or Firm:
Masatomo Sugiura
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