Title:
OSCILLATING CIRCUIT
Document Type and Number:
Japanese Patent JPS63212285
Kind Code:
A
Abstract:
PURPOSE:To obtain a reference clock signal effectively avoiding the generation of a jitter by removing a horizontal synchronizing pulse from a horizontal synchronizing signal used for comparing a phase during a prescribed period. CONSTITUTION:A synchronizing separating circuit 11 outputs the horizontal synchronizing signal SHD and a vertical synchronizing signal SVD based on a reference video signal SVREF. A monostable multivibrator circuit 13 outputs a gate pulse signal SGP only during a period when the timing of the rise and the fall of the horizontal synchronizing signal SHD fluctuates and a gate circuit 12 outputs a horizontal synchronizing signal SHD1 effectively avoiding the fluctuation of the phase as the reference signal for comparing the phase of a PLL oscillating circuit constituted of a phase comparison circuit 14, a voltage control oscillating circuit 15 and a frequency dividing circuit 16. Thereby, the reference clock signal SCK having no jitter locked to the horizontal synchronizing signal SHD can be obtained.
Inventors:
TADAMI MITSUSHIGE
Application Number:
JP4562787A
Publication Date:
September 05, 1988
Filing Date:
February 28, 1987
Export Citation:
Assignee:
SONY CORP
International Classes:
H04N5/95; H03K5/26; H03L7/08; (IPC1-7): H03K5/26; H03L7/08; H04N5/95
Attorney, Agent or Firm:
Kei Tanabe
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