OSCILLATION CIRCUIT - SEIKO NPC CORP

Title:

OSCILLATION CIRCUIT

Document Type and Number:

Japanese Patent JP2015132945

Kind Code:

A

Abstract:

PROBLEM TO BE SOLVED: To provide an oscillation circuit that attains low power consumption of both an oscillation CMOS inverter and a logic circuit at a subsequent stage with an influence of a change in power voltage and a temperature characteristic of a transistor suppressed.SOLUTION: A reference voltage generation circuit 10 is configured to include a NMOS transistor N1 in its current channel and generate a voltage corresponding to a threshold voltage of the NMOS transistor N1 as a reference voltage (Vtn), and an operation amplifier 20 is configured to include an offset PMOS transistor P1 in a current channel of a reverse input side (-), have an offset voltage equivalent to a threshold voltage of the PMOS transistor P1, and thereby output a voltage corresponding to a sum of the threshold value (Vtn) of the transistor N1 and the threshold value (Vtp) of the transistor P1 as a constant voltage (Vtn+Vtp). A current flowing to the reference voltage generation circuit 10 is configured to be supplied to a constant power source 40 via a current mirror circuit of a current mirror connection unit 21.

Inventors:

SATO MASATOSHI

Application Number:

JP2014003590A

Publication Date:

July 23, 2015

Filing Date:

January 10, 2014

Export Citation:

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