PURPOSE: To reduce phase difference between a control signal and an oscillation output signal at the time of restarting oscillation and to prevent malfunction occurring by fixing an output level when the oscillation is stopped by the control signal at a level a little lower or higher than amplitude at the time of performing the oscillation.

CONSTITUTION: A Pch transistor Q11 and an Nch transistor Q12 comprise an inverter circuit (MOSI), and the output level is decided by a signal from a NAND circuit ND1. When the control signal is set at an H level (oscillation operation), an output circuit 11 issues output by the circuit MOSI, thereby, the H level is assumed as a power source level, and an L level as the ground level. When the control signal set at the L level (stoppage of oscillation), the Q12 is cut off, and an Nch transistor Q13 is turned on, and the output of the circuit 11 goes to the H level, however, the level goes to the one lower than the power source level since it consists of an NMOS. Therefore, at the time of restarting the oscillation after the oscillation is stopped once, a time to discharge a capacitor C1 in a delay circuit D1 is shortened, thereby, the phase difference of an oscillation output signal for the control signal at the time of restarting the oscillation can be reduced.