Title:
配置面積を縮減し過渡電力を削減した発振回路
Document Type and Number:
Japanese Patent JP4355658
Kind Code:
B2
Abstract:
An oscillator circuit (40, 60) has a comparator circuit (48, 68) and a monitor and control circuit (50, 80). The comparator (48, 68) provides a periodic output signal. The monitor and control circuit (50, 80) controls the voltage swing of the periodic output voltage in response to monitoring a periodic input voltage. A capacitor (52, 90) is coupled between the output terminal of the monitor and control circuit (50, 80) and input terminal of the comparator (48, 68) and is sized to set the oscillation frequency. The monitor and control circuit (50, 80) functions to limit the input voltage excursions without using an attenuation capacitor (16). Eliminating the attenuation capacitor (16) provides a smaller oscillator circuit having reduced power supply current spikes and which is easier to implement.
Inventors:
Piggott, John M.
Application Number:
JP2004534431A
Publication Date:
November 04, 2009
Filing Date:
August 22, 2003
Export Citation:
Assignee:
Freescale Semiconductor, Inc.
International Classes:
H03K3/0231; H03K3/03; H03K4/06; H03K4/502
Domestic Patent References:
| JP8242146A | ||||
| JP4351007A | ||||
| JP62226711A | ||||
| JP8154041A | ||||
| JP11251878A | ||||
| JP54113283A |
Attorney, Agent or Firm:
Mamoru Kuwagaki