Title:
OUTPUT BUFFER CIRCUIT
Document Type and Number:
Japanese Patent JP3935925
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide an output buffer circuit which shifts the voltage of a high-speed output signal, while suppressing the noise due to the signal transition.
SOLUTION: In driving a PMOS transistor P1, NMOS transistors N11, N12, N13 are turned on in a state I, to cause an abrupt voltage drop on an output PMOS gate terminal AP1 and hence the PMOS transistor P1 to turn on, thereby propagating a signal with the least delay time to the next circuit. In a state II, the NMOS transistors N11, N12 are turned on to limit the slew rate of the voltage drop on the output PMOS gate terminal AP1, thereby checking the disturbance of the signal waveform. The NMOS transistors N12-N14, making each state conductive, are switched to control the bias condition of a control signal AP1, thus variably controlling the drive power of the PMOS transistor P1.
Inventors:
Suzuki Toyoki
Application Number:
JP2002057543A
Publication Date:
June 27, 2007
Filing Date:
March 04, 2002
Export Citation:
Assignee:
富士通株式会社
International Classes:
G11C11/417; H03K17/16; G06F3/00; H03F3/30; H03K4/00; H03K5/13; H03K17/687; H03K19/0175; H03K19/0944; (IPC1-7): H03K17/16; G06F3/00; G11C11/417; H03F3/30; H03K5/13; H03K17/687; H03K19/0175; H03K19/0944
Domestic Patent References:
| JP6296129A | ||||
| JP9093116A | ||||
| JP5191241A | ||||
| JP8065133A | ||||
| JP2001292056A | ||||
| JP5211430A | ||||
| JP5191258A | ||||
| JP7201188A | ||||
| JP9046201A |
Attorney, Agent or Firm:
Patent Business Corporation Cosmos Patent Office
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